The present invention relates to a laminated board for testing electronic components which is used when performing a burn-in test for maintaining electronic components such as ICs at a given temperature for a fixed period of time to evaluate the reliability of the electronic components, and more particularly the invention relates to a laminated board for testing electronic components which is capable of efficiently and accurately testing electronic components of the multikind and small quantity production type.
Recent tendency toward greater miniaturization and higher density of electronic components has been so remarkable that the functions and performances of electronic components have been enhanced considerably. For the evaluation of mass-produced electronic components, however, it is important to determine whether they are not only excellent in function and performance but also stabilized and standardized in quality. As a result, at the end of the fabrication steps of many electronic components, a burn-in test for maintaining the fabricated electronic components at a given high temperature for a given period of time to check their electric characteristics in performed with a view to determining the quality of the products and ensuring stabilization of the quality of the products. Also, in response to the reduction in the period of development of electronic components, there has been a demand for evaluating in a short period of time the reliability with respect to the functions and performances of various newly developed electronic components.
In the past, the burn-in test for reliability evaluation purposes has been performed by leaving a test board carrying thereon electronic components to be tested at rest in a thermostatic chamber preset to a given temperature. At this time, if the temperature distribution within the test chamber is not uniform, it is impossible to attain the objective of the test, that is, to ensure the standardization of quality, and therefore various contrivances for maintaining the chamber temperature constant have been made. Generally, such methods have been used that the chamber is increased in wall thickness and size to increase the chamber heat capacity and thereby to reduce the fluctuations in temperature and that the air within the chamber is forced to circulate to reduce the temperature variations among different portions within the chamber.
However, these methods have been disadvantageous in that not only the test chamber becomes a very large-scale unit with the resulting increase in the equipment cost but also much time is required for the desired temperature rise, with the result that in order to perform the burn-in test in accordance with the fabrication steps, the test chamber must always be operated continuously at a given temperature and the resulting loss is large. There is another inconvenience that each time the test is performed, the temperature profile of the test chamber is varied depending on the number of electronic components to be tested, etc.
Moreover, in view of the supply trend of ICs, while the main trend in the past has shown a multikind and mass production tendency toward mass-producing ICs of rated characteristics and allowing users to use these ICs in various combinations, the recent trend has been changing over to a multikind and small quantity production tendency centering on such kinds of ICs each intended for a particular user and having the functions of a large number of conventional general-purpose ICs, e.g., an ASIC (application specific integrated circuit) that is called for example as a gate-array IC or custom IC. Also, in the development of new ASICs designed for particular users, the development department of such ICs is required to perform tests at the laboratory stage prior to its production on the line and in this case the tests are performed on a minimum number of samples. In addition, the actual circumstances are such that almost all the OA equipment makers perform again the burn-in test after the purchasing of ICs with a view to ensuring the reliability of the ICs.
In these circumstances, while the previously mentioned test employing a thermostatic chamber is suited for performing the burn-in test on a large number (e.g., several thousands) of electronic components such as ICs at a time, a problem has arisen that where it is desired to perform the burn-in test on several to several tens electronic components at a time as occasion demands, the test efficiency of this test method is very low and it is also difficult to make stable measurements.
As an electronic component testing laminated board designed to overcome these problems, there has been known a so-called heater printed wiring board having a planner heater element. As shown by the sectional view of FIG. 4, it is constructed by laminating electric insulating layers 205a and 205b composed by epoxy glass-cloth sheets to both sides of a planner carbon-graphite heater element 203 and then bonding the laminate to a testing circuit layer 202 (copper foil circuit 202a) formed by the same procedure are used in the fabrication of the ordinary printed wiring board. Also, formed at the end portions of the carbon-graphite heater element 203 held between the electric insulating layers 205a and 205b are terminal portions from which leads are brought out to the outside and the leads 211 are connected to a power source. When performing the test, a current is supplied to the carbon-graphite heater element 203 whose electric resistance value is large as compared with metal conductors so that a considerable amount of joule heat is generated and this heat is transmitted to the testing circuit layer 202 through the electric insulating layer 205a, thereby increasing the temperature of the testing circuit layer 202 to a given temperature.
However, this type of conventional electronic component testing laminated board is disadvantageous in that since a heater element laminated to a testing circuit layer is held between electric insulating layers which are low in heat conductivity and thick, the transmission of heat to the testing circuit layer is slow, that is, not only the temperature rise is slow but also the dispersion of the heat from the heater element does not take place rapidly, thus tending to cause a local high temperature portion and thereby making it difficult for the temperature distribution on the surface of the testing circuit layer to become uniform.
In addition, although it is reinforced by the glass cloth, the large part of the board is composed of an organic material and therefore its mechanical strength is low. (The electric insulating layers cannot be made very thin from the viewpoint of mechanical strength thereof.) Also, as mentioned previously, the heat generated from the heater element tends to be retained in the electric insulating layers and thus the epoxy resin forming the electric insulating layers tend to be deteriorated by the heat. As a result, the continuous maximum working temperature is as high as 120.degree. C. at the surface of the testing circuit layer and thus the board cannot be used in the burn-in test under the conditions of 150.degree. C. and 125.degree. C. which are determined by the JIS specifications. There is another disadvantage that during the test the board is deformed due to the differences in thermal expansion coefficient among the respective layers and it cannot regain its original size and shape.
There is still another disadvantage that there are cases where the ICs or the like subjected to the test are operated erroneously by the electromagnetic noise produced during the on-off operation of the heater circuit layer, thus making it impossible to accurately evaluate the reliability.